1. Field of the Invention
The present invention relates to a semiconductor device in which thin silicon portions are formed by electrochemical stop etching and to a method of producing the same.
2. Description of the Related Art
In recent years, electrochemical stop etching technology has been employed in which, in forming a thin silicon portion on a semiconductor wafer, the etching is automatically stopped when the thickness of the thin silicon portion has reached a predetermined value. According to this electrochemical stop etching, a voltage fed from an external unit is controlled so that the thickness of the thin silicon portion is a desired value.
Described below, with reference to the drawings, is a wafer structure constituting a conventional semiconductor device used in the electrochemical stop etching technology. Also described below is a case where, for example, a diaphragm is formed as a thin silicon portion by electrochemical stop etching.
FIG. 7 is a plan view which schematically illustrates a semiconductor wafer 19, wherein a plurality of product chips (hereinafter referred to as chip patterns) 20, on which a diaphragm of a predetermined thickness will be formed (not shown), are provided on the surface of the wafer with scribes 21 between them, and a high N+ concentration region 22 (hereinafter referred to as low-resistance layer) is formed in the periphery of the wafer to surround all the chip patterns 20.
FIG. 8 illustrates, in cross section, the constitution between the chip patterns 20 in the semiconductor wafer 19, and is a sectional view along B-B of FIG. 7. An N-type epitaxial layer 23 is provided in the scribe regions between the chip patterns 20, a low-resistance layer 24 is provided as in the periphery of the wafer, and aluminum wiring 25 for etching are formed directly on the low-resistance layer 24. A positive voltage is fed from an external unit to the aluminum wirings 25 for etching in order to form a diaphragm (not shown) on the predetermined portions of the chip patterns 20 by etching. In the periphery of the chip pattern 20, furthermore, an aluminum wiring 26 for grounding (hereinafter referred to as GND aluminum wiring) is provided on a field oxide film 27 being connected to the isolation 28 (P+) region. The field oxide film 27 is formed on a predetermined portion other than the scribe region.
The low-resistance layer 24 is diffused in the scribe region because, even if the aluminum wiring 25 for etching is broken due to photo-defects or scars, the voltage is reliably applied to the N-epitaxial layer (not shown) of the diaphragm region in the chip pattern 20 by utilizing the low-resistance layer 24 during the etching. Furthermore, the field oxide film 27 is not formed on the whole scribe region from the standpoint of preventing a reduction in the life of the blade (not shown) during the cutting of the semiconductor wafer into dices in a subsequent step.
By employing the above-mentioned wafer structure, a voltage the same as the external voltage is applied to the epitaxial layer in the diaphragm-forming portions of all the product patterns.
By using the semiconductor wafer 19 of this constitution, the electrochemical stop etching is carried out by using the means shown in FIG. 9. The semiconductor wafer 19 is covered on its non-etching surface with a protection film 29 such as wax or the like, and is secured to a ceramic plate 30. In this state, the semiconductor wafer 19 is immersed in an etching solution 31 such as KOH in a manner that at least the portions to be etched are completely immersed therein. The low-resistance layers 22 or the aluminum wirings 25 for etching in the periphery of the wafer are directly connected to a platinum electrode 32, so that the positive voltage is supplied to the N-epitaxial layer of the diaphragm region in the chip pattern 20. Here, a negative voltage is applied to another platinum electrode 33 immersed in the etching solution 31. Thus, a diaphragm is formed in the chip patterns 20 of the semiconductor wafer 19.
According to the above-mentioned conventional semiconductor device, however, the following problems occur in the production process.
A first problem is that aluminum remains on a stepped portion of the oxide film between the aluminum wiring 25 for etching and the GND aluminum wiring 26, which makes it difficult to obtain a diaphragm of a desired thickness.
This state will be described with reference to FIG. 10(A).
The aluminum wirings 25 for etching and GND aluminum wiring 26 are deposited by aluminum vaporization or sputtering, and are patterned by using a photoresist. The GND aluminum wiring 26 is connected to the P-type substrate 34 via the field oxide film 27. Therefore, the aluminum wirings 25 for etching and the GND aluminum wiring 26 have different heights, and a step 35 of about 1 .mu.m develops in the oxide film between them. When the aluminum wiring is subjected to the photo-etching, therefore, the resist fails to acquire a constant thickness at the stepped portion 35 of the oxide film. Therefore, there results a lack of exposure to light, and whereby resist remains and aluminum 36 remains on this portion as indicated by a broken line in the drawing. Thus, the GND aluminum wiring 26 and the aluminum wiring 25 for etching are short-circuited by the aluminum remainder 36.
When the etching is effected in this state, a current passage 37 is established as indicated by an arrow in the drawing since the GND aluminum wiring 26 is connected to the P-type substrate 34, and a current leaks toward the P-type substrate 34. Then, the potential rises at the leaking portion of the P-type substrate 34, and the thickness of the diaphragm becomes larger than the desired thickness around the short-circuited portion.
A second problem is that the low-resistance region 24 on the scribe 21 is connected to the isolation 28 in the product pattern due to photodefect making it difficult to obtain a diaphragm of a desired thickness as in the above-mentioned first problem.
This state will be described with reference to FIG. 10(B).
The low-resistance region 24 formed on a predetermined portion of the scribe region is obtained by using a photoresist, patterning a masking material and selectively dispersing impurities. When photodefect occurs in the production process, however, the low-resistance layer 24 on the scribe 21 and the isolation 28 in the chip pattern 20 are often short-circuited. In this case, the breakdown voltage at the short-circuited portion is about 5 V. Here, the above-mentioned short-circuiting is not a problem if as the electrochemical stop etching is carried out at a voltage which is not higher than the breakdown voltage.
When the thickness of the diaphragm is to be controlled by feeding a voltage from an external unit, however, a voltage of, for example, 7 V which is larger than the breakdown voltage will be applied to the aluminum wiring 25 for etching in order to obtain diaphragm having a desired thickness. In this case, however, a current passage 38 is formed as indicated by arrow in the drawing, and a current leaks from this portion toward the P-type substrate 34.
Even in this case, therefore, the thickness of the diaphragm becomes larger than a desired thickness around the short-circuited portion for the same reason as that of the above-mentioned first problem.
In a process which executes electrochemical stop etching relying upon the wafer structure of the conventional semiconductor device as described above, the wafer is not of acceptable quality or a chip pattern at that portion must be excluded if short-circuiting develops due to the remaining aluminum. Moreover, when it is attempted to obtain diaphragm having a desired thickness by feeding from an external unit a voltage larger than the breakdown voltage at which the low-resistance layer and the isolation layer are short-circuited and, when short-circuiting occurs, the wafer is not of acceptable quality or the chip pattern of this portion must be excluded.
Another problem arises in relation to the electrochemical stop etching technology that is employed for forming the above-mentioned diaphragms. Electrochemical stop etching technologies have been disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. 4-239183 and Japanese Patent Publication (Kokoku) No. 4-50736 and these technologies will now be described in detail with reference to FIGS. 16 and 17. FIG. 16 is a plan view of a silicon wafer 200 of before the electrochemical etching is executed, and FIG. 17 is a sectional view along the line A--A in FIG. 16. An N-type epitaxial layer 202 is formed on a P-type silicon substrate 201, and is equipped with a diaphragm-forming region 203 and a peripheral circuit region 204. Four P-type impurity diffusion regions (piezo resistance layers) 205, 206, 207 and 208 are formed in the N-type epitaxial layer 202 on the diaphragm-forming region 203. The P-type impurity diffusion regions (piezo resistance layers) 205, 206, 207 and 208 are connected in bridge as shown in FIG. 18, a voltage Vcc is applied to a first connection terminal a, ground potential is applied to a second connection terminal b, and output Vout is taken out from third and fourth connection terminals c and d to an amplifier OP1. The amplifier OP1 is formed in a peripheral circuit region 104 in FIG. 17 and is constituted by elements such as NPN transistors 109 and the like which are isolated by a PN junction. On the surface of the silicon wafer 200 is extended, close to the scribe line, aluminum wiring 210 for ground potential to provide a ground potential at the PN junction and to provide a ground potential for the bridge of FIG. 18. To etch the P-type silicon substrate 201, furthermore, a voltage must be applied from the external unit. For this purpose, an aluminum wiring 211 for etching extends on the scribe line, and an aluminum wiring 212 is extended from the aluminum wiring 211 to the N-type epitaxial layer 202 in the diaphragm-forming region 203. In order to carry out the electrochemical etching, the silicon wafer 200 is immersed in an etching solution, a voltage is applied to the aluminum wirings 211 and 212 in order to remove the P-type silicon substrate 201 in the diaphragm-forming region 203 and to form a diaphragm.
However, the aluminum wirings 210, 211 and 212 have been formed by forming an aluminum film on the whole surface of the silicon wafer 200 and by simultaneously effecting the photo-etching using a piece of mask. Therefore, if a photodefect exists (e.g., defect caused by scars in the mask or particles) at the time of etching the aluminum wirings 210, 211 and 212, the aluminum wiring 210 for ground potential and the aluminum wiring 212 for etching are often short-circuited due to remaining aluminum 213 shown in FIGS. 16 and 17. Then, a current leaks from the aluminum wiring 211 for etching to the P-type silicon substrate 201 through aluminum wiring 210 for ground potential during the electrochemical etching. The occurrence of leakage current causes the potential of the P-type silicon substrate 201 to rise, resulting in the interruption of etching which makes it difficult to obtain a diaphragm having a desired thickness. That is, referring to FIG. 19, when a short-circuit does not take place during the electrochemical etching, the applied voltage abruptly decreases at the PN junction portion and a minimum etching potential Vth exists in the PN junction portion. Therefore, the etching stops at the PN junction portion. When the short-circuit occurs, however, the voltage distribution gradually decreases in the P-type silicon substrate 201 as represented by a broken line, the minimum etching potential Vth is set at a level corresponding to an intermediate thickness of the P-type silicon substrate 201, and the etching stops at a portion corresponding to the minimum etching potential Vth, making it difficult to obtain a diaphragm having a desired thickness.
According to the prior art as described above, the yield is inevitably low in the process for forming diaphragms using electrochemical stop etching.
In a conventional integrated pressure sensor in which a diaphragm is formed by an electrochemical stop etching, an N-type layer is disposed on a P-type substrate and has a chip isolating layer of a P-type material or an insulating material extending from the surface of the N-type layer to the P-type substrate and surrounding the entire side wall of a chip region (having an N-type epitaxial layer in which a diaphragm and an integrated circuit are formed), to isolate the chip region from a scribe region for scribing. The chip isolating layer may either be formed in the entire scribe region or may have a small width with the scribe region being an N-type layer.
When the N-type layer (the chip region) having a reduced thickness is isolated by the chip isolating layer from the chip side wall, special measures must be taken to apply an identical voltage to the N-type layers of the reduced thickness regions of the respective chips during electrochemical stop etching. To this end, it was conventionally necessary that an etching voltage applying wiring be provided on a wafer with an insulating layer interposed therebetween and be connected to the respective reduced thickness regions, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 4-39969.
FIG. 61 schematically illustrates an example of the etching voltage applying wiring. The reference numeral 600 denotes a chip isolating layer, 600 a chip region, 602 a scribe region, 603 a main line of an etching voltage applying wiring, 604 a branch line branched from the main line 603 and connected to an N-type layer of a reduced thickness in a chip region 601 via an insulating film not shown.
An inspection pad 605 is formed in the intermediate portion of the branch line 604 and is formed in the same process step as that in which the main line 603 and the branch line 604 are formed. Prior to electrochemical stop etching, a protective insulating film is formed to cover the etching voltage applying wiring and has an opening above the inspection pad 605 to expose the inspection pad 605. After the electrochemical stop etching, preferably after scribing, a inspection probe is brought into contact with the inspection pad, a high voltage is applied to an N-type layer of a diaphragm region, and a P-type substrate is then grounded to check junction leakage current therebetween for judging whether the electrochemical stop etching has been satisfactorily conducted. The judgment is easily done, because, if the electrochemical stop etching is incomplete, a large unetched area of a P-type substrate must be retained in contact with the N-type layer of the diaphragm to provide a remarkably increased PN junction area in comparison with that obtained by a normal or complete etching and the leakage current is also increased.
However, there still remains a problem that the chip yield of a wafer is sharply reduced when electrochemical stop etching is used to form a reduced thickness region in the chip region in a wafer in which a chip isolating layer is formed surrounding the side walls of the chip region, followed by scribing of the wafer into many chips.
The present invention, therefore, was accomplished in order to solve the above-mentioned problems and its object is to provide a method of etching semiconductor wafers while suppressing variance in the etching as a result of efficiently applying a desired voltage to all of the chip patterns.
Another object of the present invention is to provide a method, of producing semiconductor devices, which is capable of reliably forming a thin portion having a predetermined thickness by preventing the leakage of current from the conductor for electrochemical etching to the P-type silicon substrate.
A further object of the present invention is to favorably carry out the electrochemical stop etching without permitting the occurrence of current leakage that is caused by remaining aluminum.
A still further object of the present invention is to favorably carry out the electrochemical stop etching irrespective of the application of a voltage by avoiding a short-circuit between the low-resistance layer in the scribe region and the isolation.
Therefore, the fifth object of the present invention is to provide a semiconductor device in which the chip yield is remarkably improved and which is advantageously applied in the production of semiconductor dynamic sensors such as a semiconductor pressure sensor.